Senior Digital Design Engineer

Efficient is seeking a Senior Digital Design Engineer to join our growing team and help build the world’s most energy-efficient, general-purpose processor. In this role, you will drive the design, implementation, and verification of critical hardware features, working closely with an interdisciplinary team across architecture, physical design, verification, and software. This is a unique opportunity to contribute directly to our product roadmap and shape the future of Efficient’s technology.

Key Responsibilities

• Own feature development from specification through RTL design, implementation, and synthesis.
• Implement product features targeting both silicon and FPGA platforms.
• Develop robust unit testbench infrastructure and contribute to verification strategies.
• Design memory subsystems and integrate memory macros (SRAM, MRAM, etc.).
• Integrate and interface vendor-provided IP with custom RTL designs.
• Use industry-standard EDA tools across the full digital design flow (Cadence, Synopsys, Siemens/Mentor, ANSYS).
• Collaborate with physical design to resolve RTL issues and ensure high-quality tape-out.
• Partner with verification, software, and compiler teams to implement features that cross the hardware–software boundary, including support for Efficient’s dataflow ISA.
• Produce high-quality design documentation and participate in design reviews.
• Provide mentorship to junior engineers and contribute to best-practice development processes.

Required Qualifications

• 10+ years of post-graduate digital design experience, including substantial tape-out experience.
• Strong proficiency in RTL design and feature implementation.
• Experience running full digital design flows using industry-strength EDA tools.
• Experience integrating external or vendor IP into custom RTL.
• Hands-on experience with pre-silicon verification, including testbench development.
• Familiarity with continuous integration flows for hardware and digital design.
• Experience with version control and scripting languages (Python preferred).
• Experience working with memory compiler toolchains.
• Excellent attention to detail, strong communication, and ability to drive complex features independently.

Desired Qualifications

• Knowledge of computer architecture and/or compiler design.
• Familiarity with physical design and ASIC implementation flows.
• Experience with power/energy analysis tools (e.g., PowerArtist, Joules).
• Bachelor’s degree required; Master’s or PhD preferred.

We offer a competitive salary for this role, generally ranging from $180,000 to $220,000, along with meaningful equity and comprehensive benefits. The final compensation package will be based on your experience and location, with some flexibility to ensure we align with the right candidate.