Jeeva is an IoT solutions company enabling the next wave of connected devices. Jeeva’s unique technology provides low cost, small form factor, and orders of magnitude lower power consumption, while achieving long operating range and high reliability. Jeeva is searching for high performing, dedicated individuals to help us blaze new trails. 

---ROLE & RESPONSIBILITIES---

Jeeva is looking for a motivated digital ASIC design engineer to join our core engineering team. As a senior member of Jeeva’s ASIC design team, you will be architecting, implementing, optimizing, and testing/validating digital logic designs which power future iterations of Jeeva’s Parsair low-power wireless integrated circuit. With multiple planned tapeouts per year, Jeeva will be moving quickly, and relying on your experience and expertise to lead the digital ASIC workflow to build wireless communication systems consuming microwatts of power. 

The position requires proven low-power ASIC design experience and a willingness to jump in and do what’s needed for the success of the project. You will become part of a small but fast-moving cross-functional engineering team with significant existing design expertise and high expectations. Self-starters and those with interest in and experience in both individual contributorship and technical leadership will be highly valued in this role. You will be using industry standard ASIC design tools, and will be expected to write well-documented RTL and use version control systems. 

---MINIMUM QUALIFICATIONS---

• Master’s or PhD in electrical or computer engineering

• 5+ years of direct experience in digital ASIC design with deep knowledge of whole IC design flow from RTL coding, synthesis, static timing analysis, logic equivalence checking to post-layout verification.

• Experience in low power digital ASIC design practices including power gating, clock gating, sub-threshold operation, dynamic voltage scaling and other power reduction optimizations

• Experience using Cadence or equivalent EDA digital front end tools for simulation, synthesis, power optimization and layout (e.g., Xcelium, Genus, Joules)

• Experience working in multi-clock domain systems and verifying clock domain crossing interconnects

• Unit- and system-level verification test design and implementation

• Strong version control and code documentation habits

---PREFERRED QUALIFICATIONS---

• Wireless protocols PHY and MAC layer understanding 

• Experience with FPGA based prototyping, testing and verification for pre-tapeout validation

• Experience architecting bus-driven systems around AMBA APB or similar

• Back-end physical synthesis and verification flow experience

• Python skills

With our unique technology, Jeeva is positioned to develop myriad applications of wireless connectivity that are poorly served by conventional wireless solutions. Join our mission to capture this opportunity and reimagine the possibilities of wireless connectivity.

Jeeva is committed to a friendly and welcoming working environment and has a comprehensive benefits package. Jeeva does not discriminate based on race, gender, age, religious affiliation, or any other legally protected status.

Jeeva is located in Seattle, Washington. Please contact [email protected] to apply.