Jobs at K2 Space Corporation

Design and build mission‑critical full‑lifecycle applications connecting engineering, manufacturing, and operations. Lead architecture, deployment, and quality processes; develop prototypes to production, drive data‑led prioritization, mentor staff, and collaborate across teams to scale satellite design, production, and mission operations.

Design and implement low-level, real-time embedded software in Rust/C/C++ for satellite subsystems (propulsion, attitude, power). Lead hardware bring-up, debug complex HW/FW issues with JTAG/SWD and scopes, scale software across products, and mentor engineers to ensure fault-tolerant, flight-ready systems.

Lead development and execution of verification plans for block-to-full-chip ASICs. Build SystemVerilog/UVM testbenches, write SVAs, integrate formal methods, run constrained-random and directed tests, manage regressions and CI, perform failure triage and root-cause analysis, ensure coverage closure, support silicon bring-up and post-silicon validation, and drive DV methodology and cross-functional verification efforts.

Design, implement, verify, and maintain FPGA firmware (VHDL/SystemVerilog) for spacecraft subsystems (propulsion, attitude, RF, power). Own architecture, validate via simulation, bench and Hardware-In-The-Loop testing, support integration/troubleshooting, and build tools/infrastructure for reliable, high-reliability FPGA solutions.

Lead full physical design flow for complex SoC blocks and top-level integration—from synthesis through GDSII—achieving timing closure, PPA optimization, sign-off (DRC/LVS, IR/EM, power), automation and scripting, vendor coordination, ECO/tapeout support, and production/spaceflight support for mixed-signal, space-qualified SoCs.

Design and implement real-time, fault-tolerant flight software for high-power spacecraft. Develop control applications for propulsion, guidance/attitude, power, and communications. Create state machines, verification tools, and infrastructure for deployment and testing. Perform data analysis, anomaly investigation, and support subsystem integration and hardware-in-the-loop validation.

Build and extend ground software used to build, test, and operate K2 satellites and customer payloads. Collaborate with Mission Operations and Flight Software to design mission architecture; implement backend and frontend features (Rust, TypeScript/Vue); support on-call operations; mentor engineers and participate in design and code reviews to scale mission automation and constellation operations.

Lead development of behavioral models and mixed-signal verification methodology for SoC and subsystem verification. Create Verilog/Verilog-AMS/SystemVerilog models, build co-simulation testbenches, integrate AMS into UVM digital environments, support architectural exploration, and collaborate with analog/RF and digital teams through design reviews and silicon bring-up.

Lead end-to-end ASIC package architecture for FC-BGA and MCM solutions, driving trade studies, substrate stack-ups, SI/PI and thermal strategy, vendor engagement, qualification, and production ramp while defining organizational packaging standards and co-optimizing with silicon, RF, and systems teams.

Lead DFT architecture and implementation for complex mixed-signal SoCs. Own RTL-level scan/MBIST/LBIST insertion, ATPG flow development, coverage closure, pattern optimization, and DFT verification/signoff. Integrate mixed-signal test strategies, collaborate with RTL/DV/PD teams, support silicon bring-up and failure analysis, and improve DFT methodology and automation.

Define and execute verification plans for block-to-full-chip, build SystemVerilog/UVM testbenches, write assertions, run constrained-random and directed tests, manage regressions and CI, perform coverage closure and debug, support silicon bring-up and post-silicon validation, and collaborate across architecture, RTL, DFT, firmware, and physical design teams.

Lead ASIC package architecture and detailed FC-BGA/MCM design for high-pin-count, power-dense SoCs. Drive package trade studies (SI/PI, thermal, manufacturability), define standards, partner with silicon/RF teams, engage OSATs and vendors, and support qualification and production ramp.

Lead end-to-end RTL-to-GDSII physical implementation for high-performance SoCs for satellites. Drive timing closure, PPA optimization, tool/flow decisions, manage external PD partners, collaborate with packaging, DFT, and post-silicon teams, and support production and spaceflight tapeouts in advanced FinFET nodes.

Develop and execute verification plans for block, subsystem, and full-chip designs. Build SystemVerilog/UVM testbenches, write SVAs, integrate formal checks, run constrained-random and directed tests, manage regressions and CI/simulation farms, perform failure triage and root-cause, implement coverage closure, and collaborate across RTL, DFT, firmware, and silicon validation teams.

Lead ASIC package architecture and detailed FC-BGA/MCM package designs for high-pin-count, high-speed, power-dense SoCs. Drive package trade studies (SI/PI, thermal, manufacturability, reliability), define standards, collaborate with silicon/RF/systems teams, work with OSATs and substrate vendors, and support qualification and production ramp.

Lead end-to-end RTL-to-GDSII physical design for high-performance SoCs in advanced FinFET nodes. Own synthesis, floorplanning, P&R, CTS, STA, DRC/LVS and sign-off; develop methodologies and automation to optimize PPA; drive timing closure, coordinate package/SI/PI and DFT, manage external PD partners and EDA tool flows, and support post-silicon bring-up and production for spaceflight-qualified designs.

Lead full physical design flow for complex SoC blocks and top-level integration from synthesis to GDSII. Drive timing closure, PPA optimization, physical sign-off (DRC/LVS, IR drop, EM), ECOs and tapeout. Collaborate with front-end, verification, DFT, packaging teams and external vendors, develop automation and methodology, and support products through production and spaceflight.

The role involves leading ASIC package design for FC-BGA and MCM solutions, ensuring high-performance mixed-signal/digital SoCs succeed from architecture to production. Responsibilities include trade studies, design standards, and vendor collaboration.

Lead verification of custom ASIC/SoC from block to full-chip: develop verification plans, build SystemVerilog/UVM testbenches, run constrained-random and directed tests, use SVA and formal methods, manage regressions and CI, drive coverage closure, support post-silicon bring-up, and influence DV methodology across cross-functional teams.

Define and execute verification plans for block-to-full-chip ASICs using SystemVerilog/UVM. Build testbenches, assertions, constrained-random and directed tests, manage regressions and CI, run simulations, triage failures, close coverage, and support silicon bring-up and post-silicon debug while collaborating across architecture, RTL, DFT, firmware, and physical design teams.