Jobs at K2 Space Corporation

Design and implement low-level, real-time embedded software in Rust/C/C++ for satellite subsystems (propulsion, attitude, power). Lead hardware bring-up, debug complex HW/FW issues with JTAG/SWD and scopes, scale software across products, and mentor engineers to ensure fault-tolerant, flight-ready systems.

Build and extend ground software used to build, test, and operate K2 satellites and customer payloads. Collaborate with Mission Operations and Flight Software to design mission architecture; implement backend and frontend features (Rust, TypeScript/Vue); support on-call operations; mentor engineers and participate in design and code reviews to scale mission automation and constellation operations.

Define and execute verification plans for block-to-full-chip, build SystemVerilog/UVM testbenches, write assertions, run constrained-random and directed tests, manage regressions and CI, perform coverage closure and debug, support silicon bring-up and post-silicon validation, and collaborate across architecture, RTL, DFT, firmware, and physical design teams.

Lead full physical design flow for complex SoC blocks and top-level integration—from synthesis through GDSII—achieving timing closure, PPA optimization, sign-off (DRC/LVS, IR/EM, power), automation and scripting, vendor coordination, ECO/tapeout support, and production/spaceflight support for mixed-signal, space-qualified SoCs.

Lead development and execution of verification plans for block-to-full-chip ASICs. Build SystemVerilog/UVM testbenches, write SVAs, integrate formal methods, run constrained-random and directed tests, manage regressions and CI, perform failure triage and root-cause analysis, ensure coverage closure, support silicon bring-up and post-silicon validation, and drive DV methodology and cross-functional verification efforts.

Design and implement real-time, fault-tolerant flight software for high-power spacecraft. Develop control applications for propulsion, guidance/attitude, power, and communications. Create state machines, verification tools, and infrastructure for deployment and testing. Perform data analysis, anomaly investigation, and support subsystem integration and hardware-in-the-loop validation.

Design and build mission‑critical full‑lifecycle applications connecting engineering, manufacturing, and operations. Lead architecture, deployment, and quality processes; develop prototypes to production, drive data‑led prioritization, mentor staff, and collaborate across teams to scale satellite design, production, and mission operations.

Lead DFT architecture and implementation for complex mixed-signal SoCs. Own RTL-level scan/MBIST/LBIST insertion, ATPG flow development, coverage closure, pattern optimization, and DFT verification/signoff. Integrate mixed-signal test strategies, collaborate with RTL/DV/PD teams, support silicon bring-up and failure analysis, and improve DFT methodology and automation.

Design, implement, verify, and maintain FPGA firmware (VHDL/SystemVerilog) for spacecraft subsystems (propulsion, attitude, RF, power). Own architecture, validate via simulation, bench and Hardware-In-The-Loop testing, support integration/troubleshooting, and build tools/infrastructure for reliable, high-reliability FPGA solutions.

Lead end-to-end RTL-to-GDSII physical implementation for high-performance SoCs for satellites. Drive timing closure, PPA optimization, tool/flow decisions, manage external PD partners, collaborate with packaging, DFT, and post-silicon teams, and support production and spaceflight tapeouts in advanced FinFET nodes.

Lead FPGA prototyping and silicon bring-up for next-generation communications ASICs. Develop FPGA platforms, support first-silicon debug and validation, build automated test infrastructure, validate high-speed digital interfaces, create traffic generators and protocol checkers, and collaborate with ASIC, firmware, software, systems, and DFT teams to accelerate product development.

Design, implement, and verify flight software for high-power satellites using Rust or C/C++. Build real-time, fault-tolerant control systems, drivers for microcontrollers and sensors, state machines, CI/CD tooling, and test infrastructure including hardware-in-the-loop. Support integration, testing, anomaly investigation, and on-orbit operations.

Build and maintain ground software used to build, test, and operate K2 satellites and customer payloads. Develop backend and frontend features (Rust, TypeScript/Vue), implement mission automation, collaborate with Mission Operations and Flight Software, support on-call operations, and mentor engineers.

Lead bring-up, deployment, and optimization of full-chip and system-level emulation platforms. Build models, transactors, and BFMs; optimize emulation performance; enable HW/SW co-development; support DV, firmware, silicon bring-up, and cross-functional debug; maintain automation and CI for regression and compile flows.

Lead full physical design flow for complex SoC blocks and top-level integration from synthesis to GDSII. Drive timing closure, PPA optimization, physical sign-off (DRC/LVS, IR drop, EM), ECOs and tapeout. Collaborate with front-end, verification, DFT, packaging teams and external vendors, develop automation and methodology, and support products through production and spaceflight.

Lead end-to-end RTL-to-GDSII physical design for high-performance SoCs in advanced FinFET nodes. Own synthesis, floorplanning, P&R, CTS, STA, DRC/LVS and sign-off; develop methodologies and automation to optimize PPA; drive timing closure, coordinate package/SI/PI and DFT, manage external PD partners and EDA tool flows, and support post-silicon bring-up and production for spaceflight-qualified designs.

Lead verification of custom ASIC/SoC from block to full-chip: develop verification plans, build SystemVerilog/UVM testbenches, run constrained-random and directed tests, use SVA and formal methods, manage regressions and CI, drive coverage closure, support post-silicon bring-up, and influence DV methodology across cross-functional teams.

Lead DFT architecture and implementation for complex mixed-signal SoCs. Responsible for RTL-level scan and BIST insertion, ATPG flow development and coverage closure, mixed-signal test strategies, DFT verification and signoff, silicon bring-up support, and methodology/automation improvements while collaborating with design, verification, and physical design teams.

Define and execute verification plans for block-to-full-chip ASICs using SystemVerilog/UVM. Build testbenches, assertions, constrained-random and directed tests, manage regressions and CI, run simulations, triage failures, close coverage, and support silicon bring-up and post-silicon debug while collaborating across architecture, RTL, DFT, firmware, and physical design teams.

Own FPGA prototyping and silicon bring-up for next-generation communications ASICs. Build FPGA-based platforms, support first-silicon debug, validate high-speed interfaces, develop automated test infrastructure, and collaborate across ASIC, firmware, software, and systems teams.