Top Remote Senior Level Hardware Engineer Jobs in Seattle, WA

The Senior Package Layout Engineer will collaborate with teams to design IC substrates, optimize layouts, and improve productivity using Cadence tools.

Responsible for evaluating and ordering manufacturing equipment, overseeing installation and maintenance, providing technical support, and writing maintenance schedules.

Seeking an experienced DFT Verification Engineer to ensure ASIC DFT logic correctness, building robust verification environments, and collaborating with design engineers on high-quality silicon delivery.

The Staff Process Integration Engineer will lead process development for superconducting IC fabrication, optimize production processes, and enhance reliability in collaboration with foundries.

As an ASIC Design Verification Engineer, you will develop and execute verification strategies for AI inference ASICs, ensuring functional correctness and performance, while collaborating with design and architecture teams.

Lead PCB/FPC design for consumer electronics: component placement, routing, signal and power integrity analysis, DFM, and producing fabrication/assembly packages. Manage vendors, release designs into PLM, author ECOs, and maintain ECAD libraries.

Owner of micro-architecture and RTL lifecycle for complex digital blocks. Implement RTL in SystemVerilog/Verilog, drive control logic and IP integration, support sign-off (CDC, RDC, lint, synthesis), collaborate with DV teams for closure and debug, and take full project ownership with minimal supervision.

The role involves optimizing hardware support within a software stack for AI model deployment, collaborating with teams and hardware vendors to enhance performance and portability across platforms.

The Lead RTL/FPGA Design Engineer will develop and manage high-performance coherent modems for free space optical communications, translating DSP algorithms into synthesizable RTL, ensuring compliance, and supporting integration and testing.

Seeking a Senior Physical Design Engineer with expertise in chip-level implementation, EDA tools, and low-power design to enhance AI hardware capabilities.