Principal Digital RTL Engineer

Roguebeam is a startup developing advanced phased array systems for communications and radar applications. We design and manufacture complete systems in-house—RF, antenna, PCB, ASIC/digital, and DSP—giving our engineers end-to-end ownership of the technology and a direct line of sight from algorithm to deployed system.

We’re early, we’re growing fast, and the people who join us now will shape both the technology and the company.

We're looking for a Principal Digital RTL Engineer to set the architecture and technical direction for the digital control, beamforming, and interface logic at the heart of our phased-array products. As one of our earliest principal digital hires, you will define how we partition, specify, implement, and sign off digital silicon—not just execute a spec handed down to you.

You'll own the digital subsystem from architecture through RTL, synthesis/timing strategy, and silicon/FPGA bring-up, working as a peer with RFIC, antenna, and DSP leads. The decisions you make will define product capability and how the digital team scales.

• Own digital architecture for beamformer control, phase/amplitude interfaces, calibration, high-speed datapaths, and system-level digital blocks; translate system requirements into implementable micro-architecture

• Lead specification, RTL implementation strategy, and design reviews across the digital subsystem; personally implement the most critical or novel blocks

• Set coding, lint/CDC, synthesis, timing, and verification expectations; establish reusable IP, interfaces, and design methodology as the team grows

• Drive designs from architecture through synthesis, timing closure, P&R support, and silicon/FPGA validation; own technical risk and schedule for digital delivery

• Define digital interfaces, control protocols, and system-level requirements with RFIC, antenna, and DSP leads; resolve cross-domain trade-offs (latency, throughput, power, testability)

• Lead lab bring-up strategy and debug of fabricated ASICs or FPGA prototypes when digital behavior is in question

• Mentor senior and mid-level RTL engineers; represent digital design in technical strategy, customer/partner discussions as needed, and hiring

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field

• 12+ years of digital RTL / ASIC or large-FPGA design experience, including ownership of a subsystem or chip-level digital architecture

• Expert SystemVerilog/Verilog and industry-standard front-end tools (simulation, lint/CDC, synthesis, STA)

• Deep command of synchronous design, multi-clock systems, CDC, FSMs, high-speed interfaces, and timing closure on real silicon

• Multiple tape-outs or equivalent FPGA products shipped; demonstrated end-to-end ownership from architecture through bring-up

• Proven ability to set technical direction, review others' designs at a high standard, and work as a peer with RF, DSP, and implementation leads

• MSc or PhD with a focus on digital design, computer architecture, or VLSI

• Architected digital control or datapath for RF beamformers, phased arrays, MIMO, or similar high-performance systems

• Experience with high-speed serial interfaces, AXI/APB (or equivalent), low-power / multi-voltage design, and DFT-aware RTL

• Background in communications (5G/6G, satellite) or radar system requirements and performance metrics

• Built or scaled RTL methodology, automation (Python/Tcl), and a small digital design team in a startup or new product line

• Prior work taking a phased-array or multi-antenna product from concept through fielded silicon

This is a rare ground-floor opportunity. Joining a startup at this stage means your work has a direct, visible effect on whether the company succeeds—and a corresponding upside as we grow. Because we build the entire system in-house, you'll see your RTL designs integrated into real phased arrays and deployed in working systems, not handed off and forgotten. You'll have real ownership and a seat at the table on technical direction.

This position requires access to information controlled under ITAR/EAR; applicants must be U.S. persons as defined in 22 CFR 120.62.