Digital RTL Engineer

We’re looking for a Digital RTL Engineer to design the digital control, beamforming, and interface logic at the heart of our phased array solutions. As one of our early digital hires, you won’t just execute against a spec handed down to you—you’ll contribute to the architecture and design methodology behind our products and help shape how the team works as it grows.

You’ll own digital RTL design from architecture through synthesis, timing closure, and silicon/FPGA bring-up, working closely with RFIC, antenna, and DSP teams. The decisions you make will ripple through every product we build.

• Design and implement digital RTL (SystemVerilog/Verilog) for beamformer control, phase/amplitude control interfaces, calibration logic, high-speed data paths, and system-level digital blocks

• Drive designs from specification and architecture definition through RTL coding, synthesis, timing analysis, place-and-route support, and silicon/FPGA validation

• Perform functional simulation, lint, CDC analysis, and timing closure; collaborate on verification planning and coverage

• Work with RFIC, antenna, and DSP teams to define digital interfaces, control protocols, and system-level requirements

• Support lab bring-up, debug, and design iteration of fabricated ASICs or FPGA-based prototypes

• Contribute to design reviews, documentation, and the technical culture of a growing company

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field

• 3–5 years of relevant experience in digital RTL design for ASICs or FPGAs

• Strong proficiency in SystemVerilog/Verilog and industry-standard tools (e.g., Cadence/Synopsys synthesis & STA, simulation environments, lint/CDC tools)

• Solid understanding of digital design fundamentals: synchronous design, timing closure, clock-domain crossing, finite-state machines, and high-speed interfaces

• MSc or PhD with a focus on digital design, computer architecture, or VLSI

• Experience designing digital control logic for RF beamformers, phased arrays, or similar high-performance systems

• Familiarity with high-speed serial interfaces, AXI/APB buses, and low-power design techniques

• Experience taking designs through synthesis, timing closure, and post-silicon or FPGA validation

• Background in communications or radar system requirements

• Exposure to scripting (Python/Tcl) for design automation and flow development

This is a rare ground-floor opportunity. Joining a startup at this stage means your work has a direct, visible effect on whether the company succeeds—and a corresponding upside as we grow. Because we build the entire system in-house, you’ll see your digital designs integrated into real phased arrays and deployed in working systems, not handed off and forgotten. You’ll have real ownership and a seat at the table on technical direction.

This position requires access to information controlled under ITAR/EAR; applicants must be U.S. persons as defined in 22 CFR 120.62.