NVIDIA’s Silicon Co-Design Group sits at the crossroads of architecture, silicon, systems, and manufacturing, where first-principles thinking and engineering judgment at the highest level translate directly into product outcomes at scale.
We are looking for a Principal Performance and Manufacturing Architect who has built the models, defined the specs, and seen them validated through silicon. You have owned the connection between design intent and manufacturing reality, not as a reviewer or a contributor, but as the person who set the methodology and proved it worked. You turn ambiguous physical phenomena into quantified, defensible margin terms. You do not wait for data to confirm your hypothesis; you design the experiment that gets it. You improve how the organization ships products after every program.
The exceptional hire also uses AI deliberately — with proven workflow impact and the judgment to know where it compresses real work and where it introduces risk.
What you'll be doing:
Own the physics, from mechanism to margin. Build first-principles models connecting AVF, defect mechanisms, and DVFS transients to field FIT, system-level yield, and DPPM vs. coverage — calibrated per node and population shift — so every margin term in the V/F curve and P-state table is named, sourced, and defensible.
Set the screen that resolves escapes. Specify ATE and SLT voltage, frequency, and timing conditions that capture worst-case transient VF windows — making it unambiguous whether a marginal defect or timing violation is detected or escapes at every manufacturing stage.
Make the POR the authoritative source. Author the methodology document for each program and drive alignment across build, product definition, reliability, and test engineering — so every team is making decisions from the same model.
Prove the model before production. Own the per-release validation plan — split-screen experiments, sample sizes, statistical acceptance criteria, and production monitoring — through QS sign-off.
What we need to see:
BSEE / MSEE / PhD or equivalent experience, with 15+ years in the field.
Deep, hands-on understanding of how transient VF behavior develops worst-case stress conditions for marginal defects and timing violations — you know the mechanisms, not just the models.
Demonstrated experience building first-principles models connecting physical parameters to manufacturing outcomes, calibrated through real silicon.
A clear track record defining manufacturing test specifications on a shipped product, with each margin term explicitly sourced and owned.
Built and ran silicon validation experiments that proved models from NPI through production, not as a supporting contributor, but as the person who developed and was responsible for the experiments.
Ways to stand out from the crowd:
You have applied AI to production engineering workflows — model fitting, anomaly detection, and specification generation — and can describe the outcomes and the guardrails you put in place.
Worked across the VF specification and manufacturing boundary on multiple nodes and can articulate how your approach evolved as defect populations shifted.
Led multi-functional alignment on a methodology disagreement and brought the organization to a defensible, shared decision.
Delivered innovative solutions on programs where the schedule did not allow a second experiment.
The payoff is that every product NVIDIA ships goes through the systems you'll help build. If that's the kind of problem you want to work on, we'd like to talk! NVIDIA is widely considered one of the technology world’s most desirable employers — home to some of the most forward-thinking engineers in the industry. If you build models others depend on, set specifications that hold up through production, and make the next program better because of what you learned, we want to hear from you.
You will also be eligible for equity and benefits.
This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.NVIDIA Seattle, Washington, USA Office
4545 Roosevelt Way NE 6th Floor, Seattle, Washington, United States, 98105
NVIDIA Bellevue, Washington, USA Office
Bellevue, United States
NVIDIA Redmond, Washington, USA Office
Redmond, United States
Similar Jobs
.png)
What you need to know about the Seattle Tech Scene
Key Facts About Seattle Tech
- Number of Tech Workers: 287,000; 13% of overall workforce (2024 CompTIA survey)
- Major Tech Employers: Amazon, Microsoft, Meta, Google
- Key Industries: Artificial intelligence, cloud computing, software, biotechnology, game development
- Funding Landscape: $3.1 billion in venture capital funding in 2024 (Pitchbook)
- Notable Investors: Madrona, Fuse, Tola, Maveron
- Research Centers and Universities: University of Washington, Seattle University, Seattle Pacific University, Allen Institute for Brain Science, Bill & Melinda Gates Foundation, Seattle Children’s Research Institute
