Principal TPIP/HSIO Engineer

Job Overview:
As a Principal TPIP Quality Engineer you'll be the go-to expert for pre-silicon quality of our high-speed I/O (HSIO) subsystems. You'll initially work on DDR, PCIe, eUSB, then drive quality across upcoming SOCs by partnering with TPIP vendors, integration teams, and architects to ensure our DFX targets are met from simulation through silicon.
Responsibilities:
Pre-Silicon Quality Engineering

• Collaborate with IP vendors and internal integration/architecture/DV/DFT/PTE teams to achieve high silicon quality performance for HSIO blocks: DDR, PCIe, eUSB, D2D, etc.
• Drive closure on DFX metrics (test coverage, margin analysis, stuck-at/scan coverage, clock-domain checks).

Silicon-to-Simulation Correlation

• Help develop and maintain methodologies to validate that silicon behavior matches pre-silicon estimates.
• Analyze silicon measurements (eye-diagrams, BER, BIST logs) and correlate back to design and simulation data.

TPIP Council Leadership

• Chair the DDR and PCIe TPIP Councils to harmonize quality criteria, test architectures, and vendor deliverables across projects.
• Partner closely with Architecture, Integration, Validation, Package, and SIPI teams to anticipate integration challenges.

Required Skills and Experience:

• Bachelor's or Master's in Electrical Engineering or related field.
• 10+ years experience in high-speed interface design, validation, or bring-up (DDR, PCIe, SerDes).
• Proven track record in post-silicon characterization (BER, margining) and correlating with pre-silicon simulations.
• Strong scripting skills (Python, TCL) for data parsing, test automation, and result visualization.
• Excellent communication skills: able to drive technical discussions across vendors and internal teams.

Please note that no relocation package is available for this role.
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Salary Range:
$262,700-$355,400 per year
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