NVIDIA Logo

NVIDIA

Senior ASIC Design Engineer

Job Posted 4 Days Ago Reposted 4 Days Ago
Be an Early Applicant
In-Office
Santa Clara, CA
136K-265K
Mid level
In-Office
Santa Clara, CA
136K-265K
Mid level
Design and implement SoC's and GPU's, focusing on micro-architecture and GPU memory subsystem modules, while collaborating with various engineering teams.
The summary above was generated by AI

NVIDIA is seeking an outstanding Senior ASIC Design Engineer to design and implement the world’s leading SoC's and GPU's. This position offers the opportunity to have a real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of extraordinary people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.

What you’ll be doing:

  • As a key member of our design team, you will be responsible for the micro-architecture and design implementation of GPU memory subsystem modules.

  • Make architectural trade-offs based on features, performance requirements and system limitations, and deliver a fully verified design by working closely with verification engineers.

  • Deliver a synthesis/timing clean design while working with the physical design team to ensure a routable and physically implementable design.

  • Collaborate with architects, verification engineers, software engineers, and physical design engineers to accomplish your goals.

What we need to see:

  • Bachelors or Master’s Degree in Electrical Engineering or Computer Engineering, or equivalent experience.

  • At least 3 years of relevant work or research experience.

  • Highly proficient in logic design, Verilog and/or System-Verilog, with a good understanding of Computer Architecture and Digital Systems design.

  • A deep understanding of ASIC design flow including RTL design, verification, logic synthesis, timing analysis, ECO, and post silicon debug.

  • Strong interpersonal skills and an excellent teammate.

Ways to stand out from the crowd:

  • Prior design experience with arbiters, scheduling, synchronization, bus protocols, interconnect networks and/or switches.

  • Familiarity with architecture concepts and implementation of arbitration policies, interconnection routing policies/deadlock avoidance, virtual channels.

  • Interest or have prior experience in efficiency enhancement, such as, flow development and code generator.

  • Good debugging and analytical skills.

NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and talented people in the world working for us. Are you creative and autonomous? Do you love the challenge of crafting the highest performance & lowest power silicon possible? If so, we want to hear from you. Come, join our GPU ASIC team and help build the real-time, cost-effective computing platform driving our success in this exciting and quickly growing field.

The base salary range is 136,000 USD - 264,500 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.

You will also be eligible for equity and benefits. NVIDIA accepts applications on an ongoing basis.

NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

Top Skills

Asic Design
Digital Systems Design
Rtl Design
System-Verilog
Verilog
HQ

NVIDIA Seattle, Washington, USA Office

4545 Roosevelt Way NE 6th Floor, Seattle, Washington, United States, 98105

Similar Jobs

18 Days Ago
Hybrid
Malibu, CA, USA
146K-187K Annually
Senior level
146K-187K Annually
Senior level
Computer Vision • Hardware • Machine Learning • Software • Semiconductor
Lead systems engineering activities for R&D projects, requiring 30% systems engineering and 70% design experience in ASIC and FPGA. Collaborate with scientists to develop and validate requirements for complex technologies.
Top Skills: AsicCameoEnterprise ArchitectureFirmwareFpgaMagicdrawModel Based EngineeringSysmlUml
Yesterday
Santa Clara, CA, USA
220K-252K Annually
Expert/Leader
220K-252K Annually
Expert/Leader
Cybersecurity
The Senior Principal ASIC Design Engineer will own the design of complex digital logic modules, from architecture to silicon bring-up, collaborating with teams and mentoring junior engineers.
Top Skills: BashC/C++PerlPythonSystemverilogTcsh
Yesterday
Santa Clara, CA, USA
145K-235K Annually
Senior level
145K-235K Annually
Senior level
Cybersecurity
Design Verification Engineer ensures ASICs meet performance and reliability standards through verification methodologies, testing, and collaboration with various engineering teams.
Top Skills: AsicC/C++PerlPythonSystemverilogUnixUvm

What you need to know about the Seattle Tech Scene

Home to tech titans like Microsoft and Amazon, Seattle punches far above its weight in innovation. But its surrounding mountains, sprinkled with world-famous hiking trails and climbing routes, make the city a destination for outdoorsy types as well. Established as a logging town before shifting to shipbuilding and logistics, the Emerald City is now known for its contributions to aerospace, software, biotech and cloud computing. And its status as a thriving tech ecosystem is attracting out-of-town companies looking to establish new tech and engineering hubs.

Key Facts About Seattle Tech

  • Number of Tech Workers: 287,000; 13% of overall workforce (2024 CompTIA survey)
  • Major Tech Employers: Amazon, Microsoft, Meta, Google
  • Key Industries: Artificial intelligence, cloud computing, software, biotechnology, game development
  • Funding Landscape: $3.1 billion in venture capital funding in 2024 (Pitchbook)
  • Notable Investors: Madrona, Fuse, Tola, Maveron
  • Research Centers and Universities: University of Washington, Seattle University, Seattle Pacific University, Allen Institute for Brain Science, Bill & Melinda Gates Foundation, Seattle Children’s Research Institute
By clicking Apply you agree to share your profile information with the hiring company.

Sign up now Access later

Create Free Account

Please log in or sign up to report this job.

Create Free Account