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Microsoft

Senior Memory Controller RTL Design Engineer

Posted Yesterday
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In-Office
Redmond, WA, USA
120K-261K Annually
Senior level
In-Office
Redmond, WA, USA
120K-261K Annually
Senior level
Design, implement, and optimize memory controller micro-architecture in Verilog/SystemVerilog. Integrate IP into SoC, write basic tests, perform lint/CDC/low-power/timing checks, and automate tasks with scripting and AI. Collaborate cross-functionally and with IP providers to deliver high-quality, performance- and power-optimized blocks on schedule.
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Overview

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission.

The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE is responsible for design, development, manufacturing and packaging of Microsoft's state-of-the-art computer chips, notably the Azure Cobalt. Our solutions provide sustainable strategic advantage to Microsoft and enable our customers to achieve more.

As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Compute Silicon & Manufacturing Engineering team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for seasoned engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.

We are looking for a Senior Memory Controller RTL Design Engineer to join the team.


Responsibilities
  • Define and implement the micro-architectural specification in Verilog or System Verilog.
  • Refine your implementation for area, power and performance.
  • Integration of the functional IP into SoC.
  • Exercise the functionality of the block by writing basic tests.
  • Perform design quality checks such as Lint, CDC/RDC, Low Power Intent, timing QoR.
  • Automate tasks using scripting and AI for efficiency.
  • Collaborate with highly energetic cross functional team members with respect and with One Microsoft mentality to establish synergies.
  • Collaborate with IP providers.
  • Deliver high quality functional blocks on schedule and with professional integrity.
  • Challenge the status quo with your growth mindset.

Qualifications

Required/minimum qualifications

  • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience
    • OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience
    • OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience
    • OR equivalent experience. 

Other Requirements

  • Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter. 
  • This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations.  As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.

Preferred Qualifications:

  • 6 or more years designing and implementing novel high-performance DDR4 or DDR5 memory controllers
  • Background and understanding of Digital Design principles as part of SoC and/or IP development teams
  • Applied understanding of low power design princiles  
  • Highly Proficient in Verilog/System Verilog coding constructs.
  • Highly Proficient in high-speed design principles
  • Knowledge of front-end tools (Verilog simulators, Connectivity tools, CDC checkers, low power static checkers, linting)
  • Familiarity with Synthesis and STA tools
  • Ability to write scripts using Perl, Tcl, Python etc.
  • Experience with multi-bit error correction such as Reed-Solomon Encoding
  • Understanding of Industry standard interface protocols such as CHI, APB, AMBA

#SCHIE #CSME



Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $160,200 - $261,000 per year.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:
https://careers.microsoft.com/us/en/us-corporate-pay


This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.



Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.

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