Senior Quantum Analog Mixed-Signal Verification Engineer

At Microsoft Quantum, we aim to empower science and scientists to solve the world's biggest problems by realizing advanced computing platforms at the intersection of high-performance computing, artificial intelligence, and quantum information technology. Our team is dedicated to developing the first scalable, fault-tolerant quantum computer and is leading progress in areas ranging from quantum hardware and error correction to comprehensive integration with Azure. Our full-stack strategy spans the physics of quantum devices through scalable readout and control infrastructures powered by cryo-electronics. We are entering a pivotal phase of accelerated growth in quantum computing, and this position presents a unique opportunity to contribute meaningfully to a transformative technology.

As a Senior Quantum Analog Mixed-Signal Verification Engineer in the Quantum 1st Party Hardware Application-Specific Integrated Circuit (ASIC) team, you will play a critical role in advancing the development of the team's quantum Analog Simulation infrastructure. Your responsibilities will include creating and defining system-wide Analog Mixed-Signal (AMS) models, simulation environments, and test plans for the team's System-on-a-Chip (SoC) and Intellectual Property (IP) blocks, and coordinating individuals, contingent staff, and external vendors to deliver a high-quality design.

You will work across SoC architecture, quantum hardware, analog design, and physical design teams throughout the program lifecycle to bring SoC and IP into production at the quality required for scalable quantum systems. If you thrive on complex challenges and foundational technologies that redefine what's possible, we invite you to help shape the future of quantum computing. 
Microsoft’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.

• Own and drive Analog Mixed-Signal (AMS) simulation of complex analog and digital blocks, including building analog block models, preparing and executing test plans, and supporting analog and AMS verification activities through tape-out.
• Integrate analog and digital blocks across multiple SoCs to create a system-wide simulation environment for system-level algorithm modeling.
• Coordinate with Analog Verification Engineers to run block-level and top-level analog and AMS simulations. Document results, present findings, drive design resolution, and provide status reports to track program metrics.
• Build behavioral models for part or all of the analog components to support AMS verification, and provide models for full-chip digital verification.
• Coordinate with internal team members and contractors, including screening and onboarding contractors as needed to complete deliverables.
• Establish standardized AMS verification and modeling methodology with peers.
• Other
  • Embody our culture and values.  

• 10+ years of experience in analog and Analog Mixed-Signal (AMS) verification, including delivery of verified analog and mixed-signal designs into mass production.
• Hands-on experience with both analog simulation and digital simulation, and the ability to simulate them together for system-level AMS verification.
• Proficient use of Electronic Design Automation (EDA) tools from Cadence, Mentor, and Synopsys, including AMS tools such as Synopsys XA and Cadence Spectre AMS.
• Proficient in digital verification setup using Universal Verification Methodology (UVM) or Open Verification Methodology (OVM) testbenches.
• Experience working with analog blocks such as Voltage-Controlled Oscillators (VCOs), charge pumps, interpolators, bandgap references, Operational Transconductance Amplifiers (OTAs), Phase-Locked Loops (PLLs), Analog-to-Digital and Digital-to-Analog Converters (ADCs/DACs), Low-Dropout Regulators (LDOs), Serializer/Deserializers (SerDes), and other foundational analog blocks.
• Proficient in behavioral modeling for corners and variability of performance and process spread.
• Experience with silicon characterization of AMS blocks and release to production.
• Proficiency in MATLAB for complex modeling and visualization.
• Proficiency in scripting languages such as Python and Perl, including automation of simulation and data analysis environments.

Quantum Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $160,200 - $261,000 per year.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:
https://careers.microsoft.com/us/en/us-corporate-pay

This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.

Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.