Senior SOC Integration Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for a Senior SoC Integration Engineer to help achieve that mission.

The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE is responsible for design, development, manufacturing and packaging of Microsoft's state-of-the-art computer chips, notably the Azure Cobalt. Our solutions provide sustainable strategic advantages to Microsoft and enable our customers to achieve more.

As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Compute Silicon & Manufacturing Engineering team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for a Senior SoC Integration Engineer with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.

We are looking for a Senior SOC Integration Engineer to join the team to support our mission and culture. This key role will impact the organization by helping deliver cutting edge silicon.

The candidate for this position will be expected and able to complete the following responsibilities:

• Own SOC implementation and integration strategies.
• Work with SOC Integration and IP Design Engineers to ensure RTL quality and timeliness.
• Continue to assess and refine implementation for area, power, and performance.
• Integrate various functional blocks into the SOC FPGA.
• Exercise the functionality of the block by writing basic tests and debug for various features at IP and SOC levels as deemed necessary.
• Lead the gate-level simulation team to complete goals on time with high quality.
• Perform design quality checks such as Lint, CDC, RDC, Low Power Intent.
• Work with the verification team to ensure Design quality. 
• Challenge the status quo with a growth mindset.

Required Qualifications:

• Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience.

• 5+ years of technical experience/knowledge in SOC Integration.
• Demonstrated expertise in Computer Architecture, Digital Design, IP and SOC development.
• Highly proficient in Verilog/System Verilog.
• Experience with industry standard RTL tools and flows.
• Experience in high performance and low power design techniques.
• Experience in delivery of ASIC IPs, sub-systems and/or top-level SOC RTL for multiple projects.
• Experience in design flows and methodologies including Lint, CDC, RDC, synthesis, timing, and power analysis.
• Good understanding of IP development & SOC integration challenges at subsystem and full chip level.
• Experience with gate-level simulation.
• Experience with clock/reset design.
• Effective communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams.
• Proven track record of silicon delivery as a team leader.
• Experience in design for testability, debug, and manufacturing.
• Ability to write scripts using Python, Perl, Tcl, etc.
• Ability to leverage AI to improve efficiency and quality of deliverables.
• Experience in industry standard tools used for design abstraction, integration, and wiring.
• Experience in front end design flows and methodologies: SCM, RTL partitioning, third party IP integration, synthesis, CSR integration, memory map, and 1st order verification debug.
• Domain knowledge in one or more of these areas is a plus: PCIe, Fabric, Security, CPU, Coherence, high speed interfaces/protocols.

#SCHIE #CSME

Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $160,200 - $261,000 per year.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:
https://careers.microsoft.com/us/en/us-corporate-pay

This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.

Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.