Top Design Engineer Jobs in Seattle, WA

Designs and scales data center hardware platforms and automation across DigitalOcean’s infrastructure. Responsibilities include leading hardware design and vendor projects, developing hardware roadmaps, automating configuration and validation, troubleshooting fleet hardware as a Tier 3 escalation, supporting 24/7 on-call operations, improving firmware and hardware automation, collaborating with vendors, and mentoring engineers. The role requires deep server architecture, Linux, networking, storage, firmware, configuration management, and large-scale hardware automation expertise.

Designs and tests analog circuits and systems for high-performance accelerometers, from architecture through verification. Responsibilities include requirements analysis, simulations, data analysis, test procedure development, design reviews, supplier coordination, and supporting new product development within schedule and budget. The role collaborates with mechanical, systems, and manufacturing teams and reports technical status to management and customers.

Designs, develops, analyzes, tests, and maintains software systems for Boeing’s P-8 mission systems program. Responsibilities include defining and tracing requirements, developing architectures and interfaces, conducting code reviews and system analyses, monitoring verification and issue resolution, supporting certification and operational needs, creating user documentation, and coordinating software project and supplier activities.

Design and develop primary and secondary structural components for next-generation UAVs through concept, CAD modeling, detailed design, verification testing, and production release. Collaborate with multidisciplinary teams, perform hand calculations and limited FEA, produce drawings and documentation, support manufacturing and flight test, and improve structural design practices.

Design and develop primary and secondary structural components for a next-generation UAV. Perform CAD modeling, hand calculations, limited FEA, generate drawings and documentation, support validation and testing, collaborate with cross-functional teams, and iterate hardware through manufacturing and flight tests.

Design and develop primary and secondary structural components for next-generation UAVs from concept through production. Perform CAD modeling, hand calculations, limited FEA, generate drawings and documentation, support testing and validation, collaborate cross-functionally with propulsion, avionics, manufacturing, and flight test, and iterate designs for manufacturability and integration.

Design and develop primary and secondary structural components for a next-generation UAV platform from concept through production. Create CAD models and drawings, perform hand calculations and basic FEA, collaborate with cross-functional teams for system integration, support structural testing and validation, resolve manufacturing and flight-test issues, and produce engineering documentation in compliance with aerospace standards.

Design and develop primary and secondary structural components for a next-generation UAV. Execute full design lifecycle, perform hand calculations and limited FEA, collaborate across disciplines, support validation/testing, and produce design documentation and drawings to aerospace standards.

Design and release propulsion hardware for a low-bypass turbofan UAV across engine, fuel, oil, and bleed air systems. Create CAD models/drawings (Siemens NX), apply GD&T, support manufacturing, testing, BOM/configuration control, analyses (hand calcs, FEA, GFSSP, REFPROP), and collaborate with production, flight test, and cross-functional teams.

Lead design and development of primary and secondary aircraft structures for next-gen UAVs. Own CAD/FEA-driven structural lifecycle, material selection (composites/metal), testing, integration, verification, and mentor junior engineers while ensuring manufacturability and compliance with aerospace standards.

Design and develop primary and secondary structural components for a next-generation UAV. Execute full design lifecycle, perform hand calculations and limited FEA, support structural validation and testing, produce drawings and documentation, and collaborate with cross-functional teams to ensure manufacturability and system integration.

Design and release primary and secondary structural components for an autonomous UAV. Execute conceptual through production design, perform hand stress calculations, support testing and validation, collaborate across disciplines, produce drawings and documentation, and work with manufacturing and flight test to resolve issues.

Design complex PCB layouts for aircraft hardware, including digital, analog, RF, high-speed, and power electronics. Manage stack-ups, routing constraints, component placement, signal and power integrity, impedance control, thermal and EMI mitigation, and mechanical integration. Generate manufacturing documentation and collaborate with electrical, mechanical, manufacturing, and fabrication teams to ensure manufacturability, reliability, and compliance.

Design and verify analog and digital circuits for high-performance accelerometers from architecture through detailed design and testing. Perform simulations, data analysis, define and execute test procedures, present design reviews, report status, drive new product development to schedule and budget, and support factory RCCA activities while collaborating with mechanical, systems, and manufacturing teams.

Develop custom silicon IP from microarchitecture through RTL implementation, verification, signoff, and post-silicon validation. Responsibilities include PPA optimization, hardware acceleration algorithms, CDC/RDC/lint and timing closure, silicon bring-up, debugging, root-cause analysis, and mentoring engineers. The role collaborates across architecture, SoC, firmware, verification, and physical design teams to deliver high-performance, power-efficient Azure Cobalt chip solutions.

Leads physical implementation and layout of advanced-node D2D SerDes and analog/mixed-signal IP from floorplanning through tapeout and signoff. Owns matching-critical layout, parasitic control, integration, physical verification, reliability analysis, documentation, and production collateral. Collaborates with circuit, package, signal-integrity, ESD, CAD, foundry, and SoC teams while mentoring contributors and coordinating distributed partners. Develops analog layout automation and methodology improvements using scripting.

Lead systems engineering and design for large-scale FAA radio network deployments. Conduct site surveys, network configuration, requirements definition, system decomposition, trade studies, and MBSE modeling. Create installation engineering packages containing drawings, bills of materials, schematics, and procedures. Provide technical leadership, facilitate design reviews, and coordinate with FAA stakeholders, field teams, drafters, schedulers, and installation contractors while ensuring compliance with engineering standards.

Lead systems engineering and design for large-scale FAA radio network deployments. Conduct site surveys, network configuration, system decomposition, requirements definition, trade studies, and MBSE modeling. Develop installation engineering packages with drawings, bills of materials, schematics, and procedures. Provide technical leadership, facilitate design reviews, and coordinate with FAA stakeholders, deployment teams, CAD designers, schedulers, and installers while ensuring compliance with engineering and program requirements.

Lead development and delivery of physical design tool flows, methodologies, and sign-off for block, sub-chip, and full-chip levels of Microsoft Next‑Gen AI SoC. Responsibilities include PnR convergence, STA and timing ECOs, PV and FEV sign-off, global clocking, EM/IR analysis, IP collateral validation, design reviews, and mentoring junior engineers.

Design and manage production tooling for complex aerospace systems from concept through fabrication and prove-out. Responsibilities include designing fixtures, molds, gauges, carts, and protective tooling; conducting FEA and calculations; creating detailed tool packages; leading cross-functional reviews; managing fabrication and issue resolution; developing setup, maintenance, and inspection documentation; and supporting first article dimensional validation.

Design high-performance, high-bandwidth Network-on-Chip systems for AI SoCs. Responsibilities include IP microarchitecture specification, RTL development, synthesis, lint, clock-domain-crossing and formal verification closure, and SoC integration. The engineer collaborates with architecture, verification, and physical-design teams to ensure designs meet specifications. Preferred expertise includes digital design, Verilog/SystemVerilog, ASIC and SoC development, PPA trade-offs, post-silicon debugging, networking ASICs, AI fabrics, and complex control logic.

Develops and validates electromagnetic environmental effects requirements and architectures for aircraft systems. Performs E3 trade studies, modeling, simulation, EMI/EMC analyses, test automation, and aircraft-level testing involving lightning, HIRF, EMP, and precipitation static. Reviews supplier test plans, supports manufacturing and design teams, identifies compatibility issues, recommends mitigations, processes engineering data, and presents results to stakeholders. The role is fully onsite in Tukwila, Washington, with up to 25% domestic travel and Secret clearance requirements.

Designs and analyzes electromagnetic environmental effects for defense aircraft programs. Develops E3 requirements and architectures, performs modeling and trade studies, supports EMI/EMC testing, reviews supplier test documentation, develops test automation, resolves compatibility issues, and collaborates with manufacturing, suppliers, customers, and engineering teams. The role supports aircraft-level testing involving EMI, lightning, HIRF, precipitation static, and nuclear EMP environments.

Designs high-performance silicon and AI system-on-chip components, including IP microarchitecture, RTL, synthesis, and SoC integration. Collaborates with architecture, verification, and physical design teams to ensure implementations meet specifications. The role involves digital design, ASIC/SoC development, clock-domain-crossing and lint closure, PPA trade-offs, fabric or networking ASIC design, and post-silicon debugging.

Lead IP selection, acquisition, release management, and integration for AI SoC programs. Establish scalable IP release/QA processes, track third-party and internal IPs, drive pre/post-silicon issue resolution, and partner with architecture, physical design, DFT, validation, packaging, and board teams to ensure high-quality IP delivery and successful product outcomes.