Top Design Engineer Jobs in Seattle, WA

Lead full physical design flow for complex SoC blocks and top-level integration—from synthesis through GDSII—achieving timing closure, PPA optimization, sign-off (DRC/LVS, IR/EM, power), automation and scripting, vendor coordination, ECO/tapeout support, and production/spaceflight support for mixed-signal, space-qualified SoCs.

Lead end-to-end RTL-to-GDSII physical implementation for high-performance SoCs for satellites. Drive timing closure, PPA optimization, tool/flow decisions, manage external PD partners, collaborate with packaging, DFT, and post-silicon teams, and support production and spaceflight tapeouts in advanced FinFET nodes.

The job involves designing analog and mixed-signal ICs for Power Management Products, assisting in circuit synthesis, simulation, layout, and providing customer support.

As an EMC Design Engineer, you'll optimize grounding and shielding for wearable tech, ensure EMC/ESD compliance, and manage engineering projects from development to production.

Lead end-to-end physical implementation of large SoC blocks from RTL through GDS, including synthesis, floorplanning, place-and-route, timing signoff, physical verification, EMIR, formal equivalence, and low-power verification. Drive SOC clock construction and CTS, collaborate with CAD/RTL/DFT/architecture/power teams, influence PD tools and methodology, and communicate project status while owning technical delivery for medium-to-large designs.

Design and deliver FPGA-based digital subsystems for Microsoft's fault-tolerant topological quantum computer. Responsibilities include RTL development, low-latency streaming pipelines, high-speed interconnects, clocking and CDC, hardware/software co-design, verification, lab bring-up, timing closure, and CI build automation. The role collaborates with quantum physicists, software, RF/EE, and manufacturing teams while supporting quantum readout, error decoding, control, and system-scale performance.

Design and automate emulation and simulation models; develop verification environments and test suites for block, chip, and system levels; define verification plans with architects; create tests, assertions, scoreboards, and coverage models; debug testbench and emulation failures; build automation (Makefiles/scripts) and participate in CI, code reviews, and cross-functional collaboration.

Develops complex UVM/SystemVerilog and C++ verification environments for AI accelerator silicon at block, chip, and system levels. Creates verification plans, tests, scoreboards, assertions, constraints, and coverage models; debugs simulation and emulation failures; supports reference modeling and post-silicon validation. The role collaborates with architecture, design, firmware, validation, and product teams, while developing scalable scripts and Makefiles and applying Agile practices.

Verifies components for Fabric Interconnect by defining test strategies, developing UVM or formal verification environments, running simulations, debugging failures, applying constrained-random and coverage-based methods, and improving verification tools and methodologies. The role also involves collaborating with design teams, applying generative AI, and mentoring engineers. Preferred experience includes pre-silicon IP or subsystem verification, CHI/AMBA protocols, fabric interconnects, PCIe, CXL, test planning, coverage signoff, and Python scripting.

Lead verification of complex fabric interconnects or block-level designs. Define verification strategies and test plans, develop UVM/SystemVerilog environments, run and debug simulations, apply random-stimulus and coverage-driven techniques, improve verification efficiency and tools, apply generative AI to verification, and mentor/coach team members.

Develops complex pre- and post-silicon verification environments, tests, models, and coverage for AI accelerator SoCs. Creates verification plans, testbenches, scoreboards, sequences, constraints, assertions, and functional coverage; debugs simulation and emulation failures; develops scalable scripts and Makefiles; and collaborates with architecture, design, firmware, validation, and product engineering teams.

Supports the conceptualization, design, development, testing, and deployment of aerospace and defense structures, mechanisms, and mechanical systems. Responsibilities include 3D modeling, engineering drawings, calculations, supplier and component evaluation, hands-on fabrication and testing, documentation, manufacturability reviews, and production support. The role translates customer requirements into design solutions, collaborates with cross-functional teams, contributes to proposals, and mentors junior engineers. Work focuses on high-energy actuation systems and flight-worthy hardware.

Leads pre-silicon verification for custom IP and SoC designs, developing test plans, constrained-random tests, scoreboards, checkers, assertions, UVM components, and functional coverage. The role debugs simulation and emulation failures, drives coverage closure, builds verification infrastructure, collaborates across engineering teams, and mentors engineers. It focuses on AI and machine-learning SoCs and requires technical leadership across multiple product cycles.

Design, develop, test, and support aerospace flight-worthy structures, mechanisms, and mechanical systems. Create 2D/3D models, perform calculations and analyses, prepare drawings/BOMs, support manufacturing/QA/testing, assist proposals, and mentor junior engineers.

Design and develop aerospace/flight-worthy structures, mechanisms, and mechanical systems. Create 2D layouts and 3D models, perform engineering analysis, document requirements and tests, support manufacturing/QA, aid proposals, and mentor junior engineers.

Design and develop aerospace flight-worthy structures, mechanisms, and mechanical systems. Produce 2D/3D CAD models and drawings, perform basic calculations and analyses, create BOMs and QA specs, support manufacturing, testing, and deployment, and assist proposal and business development efforts.

Design, develop, test, and support aerospace/flight-worthy structures, mechanisms, and mechanical systems. Create 2D layouts and 3D models, perform mechanical analyses, select components/vendors, produce drawings/BOMs/specs, support manufacturing, testing, deployment, proposals, and mentor junior engineers.

Design, analyze, and support aerospace flight structures with emphasis on advanced composite components. Create CAD models and drawings, define BOMs and manufacturing/QA requirements, perform mechanical calculations and GD&T, support testing and production, provide customer technical support, and mentor junior engineers.

Lead mechanical design for aerospace and defense structures, mechanisms, and systems from concept through qualification. Perform calculations, tolerance stack-ups, produce CAD models and drawings, generate BOMs, support prototyping and testing, contribute to proposals, and mentor junior engineers.

Develops verification plans, simulation environments, test cases, and coverage strategies for AI silicon IPs, subsystems, and SoCs. Collaborates with architecture, design, and verification teams to debug hardware designs and close functional and code coverage. Preferred experience includes UVM, AXI, embedded processors, secure hardware, FPGA or emulation, RTL, Assembly, linker scripts, and Makefiles.

Designs conceptual, preliminary, and final high-voltage substation structures, foundations, lightning protection systems, bus systems, and factory-built structures. Prepares and reviews structural and foundation calculations, drawings, equipment specifications, and layouts for code and customer compliance. Coordinates with project managers, customers, and internal teams, supports proposals and schedules, resolves technical and construction issues, and answers customer questions.

Design, develop, analyze, and test fluid system hardware and subsystems for launch vehicles. Create CAD models, P&IDs, perform FEA and fluid modeling, develop test plans, support manufacturing, and manage multiple concurrent projects to meet customer schedules and safety requirements.

Design and standardize global lab infrastructure by translating product hosting needs into infrastructure criteria, evaluating facility capacity (power, cooling, networking), creating design-intent packages for contractors, supporting build-vs-modify decisions, using AI/automation for analysis, and coordinating design, construction, commissioning, and operational handoffs across stakeholders.

Support digital hardware specification, design, and implementation, including ASIC physical design, build-controlled releases, hardware and software evolution, documentation, change control, quality standards, and troubleshooting. Improve processes and tools, provide technical guidance, manage project resources, and collaborate with customers on technical requirements. Required expertise includes CMOS technology, physical design flows, EDA tools, scripting, timing and power analysis, Verilog HDL, third-party IP integration, and advanced process nodes.

Lead functional verification and validation of complex DPU/SoC designs across pre-silicon and post-silicon stages. Develop UVM/C testbenches, C tests and firmware, define test plans, run regressions, debug failures, create stress/performance scenarios, participate in chip bring-up, and mentor engineers while collaborating with architecture, design, and partner teams.