Top Tech Jobs & Startup Jobs in Seattle, WA

Reposted 19 Hours AgoSaved
Remote
United States
190K-285K Annually
Senior level
190K-285K Annually
Senior level
Defense • Manufacturing
The Principal ASIC Design Verification Engineer is responsible for verifying custom silicon designs, developing verification plans, and collaborating with cross-functional teams on design-for-verification practices and silicon validation.
Top Skills: CC++PerlPythonQuestaSimvisionSystemverilogTclUvmVcsVerdiXcelium
Reposted 19 Hours AgoSaved
Remote
United States
170K-250K Annually
Senior level
170K-250K Annually
Senior level
Defense • Manufacturing
The Senior ASIC Design Verification Engineer will verify custom silicon designs, develop verification plans, drive test strategies, and collaborate with various engineering teams.
Top Skills: Ci/CdGitPerlPythonQuestaSimvisionSystemverilogTclUvmVcsVerdiXcelium
Reposted 19 Hours AgoSaved
Remote
United States
130K-200K Annually
Mid level
130K-200K Annually
Mid level
Defense • Manufacturing
The ASIC Design Verification Engineer will verify silicon designs, develop verification plans, execute tests, and manage simulation environments, ensuring high quality and functionality through rigorous testing and collaboration with cross-functional teams.
Top Skills: GitPerlPythonQuestaSimvisionSystemverilogTclUvmVcsVerdiXcelium
3 Days AgoSaved
Remote
United States
160K-220K Annually
Senior level
160K-220K Annually
Senior level
Defense • Manufacturing
Develop and enhance embedded firmware for high-performance mixed-signal and digital SoCs, contributing to firmware architecture and supporting hardware bring-up and validation.
Top Skills: AssemblyCC++Rtos
Reposted 5 Days AgoSaved
Remote
United States
170K-250K Annually
Senior level
170K-250K Annually
Senior level
Defense • Manufacturing
The Senior DFT Engineer will define and implement DFT architecture for mixed-signal SoCs, lead RTL-level DFT insertion, and collaborate with design teams to ensure high test coverage and manufacturability.
Top Skills: AtpgBistBoundary ScanDft ArchitectureJtagLow-Power DftMemory BistMixed-Signal SocsRtlScan InsertionTap ControllerTest Strategies
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Reposted 5 Days AgoSaved
Remote
United States
140K-200K Annually
Senior level
140K-200K Annually
Senior level
Defense • Manufacturing
The RFIC Layout Designer will lead the implementation of RF and mixed-signal ICs, focusing on layout strategies, top-level integration, and collaborating with various teams to ensure successful silicon tapeouts.
Top Skills: Eda ToolsFinfet TechnologiesMixed-Signal Integrated CircuitsPower PlanningRficSoc Design
Reposted 8 Days AgoSaved
Remote
United States
120K-180K Annually
Senior level
120K-180K Annually
Senior level
Defense • Manufacturing
As a Senior RFIC Layout Designer, you will implement RF and mixed-signal IC layouts for satellite communication systems, focusing on layout execution and integration with cross-functional teams. Duties include ensuring layout quality, collaborating with design teams, and driving chip signoff processes.
Top Skills: CadDrcEmErcEsdFinfetIrLvsMixed-Signal IcRfic
Reposted 11 Days AgoSaved
Remote
United States
190K-260K Annually
Senior level
190K-260K Annually
Senior level
Defense • Manufacturing
The Principal GNC Engineer will drive spacecraft GNC architecture, perform verification and validation, develop tools and algorithms, and support launch operations, while mentoring engineers.
Top Skills: C/C++JuliaMatlabPython
Reposted 11 Days AgoSaved
Remote
United States
190K-285K Annually
Expert/Leader
190K-285K Annually
Expert/Leader
Defense • Manufacturing
Lead architecture and development of low-level embedded firmware for mixed-signal and digital SoCs, ensuring first-silicon success and robust firmware foundations.
Top Skills: CC++Rtos
18 Days AgoSaved
Remote
United States
190K-280K Annually
Senior level
190K-280K Annually
Senior level
Defense • Manufacturing
Lead the development of SoCs for satellites, manage physical design partners, ensure timing closure, and support design integration.
Top Skills: CadenceEdaGdsiiRtlSiemensSynopsys
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