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The Principal ASIC Design Verification Engineer is responsible for verifying custom silicon designs, developing verification plans, and collaborating with cross-functional teams on design-for-verification practices and silicon validation.

The Senior ASIC Design Verification Engineer will verify custom silicon designs, develop verification plans, drive test strategies, and collaborate with various engineering teams.

The ASIC Design Verification Engineer will verify silicon designs, develop verification plans, execute tests, and manage simulation environments, ensuring high quality and functionality through rigorous testing and collaboration with cross-functional teams.

Develop and enhance embedded firmware for high-performance mixed-signal and digital SoCs, contributing to firmware architecture and supporting hardware bring-up and validation.

The Senior DFT Engineer will define and implement DFT architecture for mixed-signal SoCs, lead RTL-level DFT insertion, and collaborate with design teams to ensure high test coverage and manufacturability.

The RFIC Layout Designer will lead the implementation of RF and mixed-signal ICs, focusing on layout strategies, top-level integration, and collaborating with various teams to ensure successful silicon tapeouts.

As a Senior RFIC Layout Designer, you will implement RF and mixed-signal IC layouts for satellite communication systems, focusing on layout execution and integration with cross-functional teams. Duties include ensuring layout quality, collaborating with design teams, and driving chip signoff processes.

The Principal GNC Engineer will drive spacecraft GNC architecture, perform verification and validation, develop tools and algorithms, and support launch operations, while mentoring engineers.

Lead architecture and development of low-level embedded firmware for mixed-signal and digital SoCs, ensuring first-silicon success and robust firmware foundations.

Lead the development of SoCs for satellites, manage physical design partners, ensure timing closure, and support design integration.