Top Tech Jobs & Startup Jobs in Seattle, WA

Lead FPGA prototyping and silicon bring-up for next-generation communications ASICs. Develop FPGA platforms, support first-silicon debug and validation, build automated test infrastructure, validate high-speed digital interfaces, create traffic generators and protocol checkers, and collaborate with ASIC, firmware, software, systems, and DFT teams to accelerate product development.

Design, implement, and verify flight software for high-power satellites using Rust or C/C++. Build real-time, fault-tolerant control systems, drivers for microcontrollers and sensors, state machines, CI/CD tooling, and test infrastructure including hardware-in-the-loop. Support integration, testing, anomaly investigation, and on-orbit operations.

Build and maintain ground software used to build, test, and operate K2 satellites and customer payloads. Develop backend and frontend features (Rust, TypeScript/Vue), implement mission automation, collaborate with Mission Operations and Flight Software, support on-call operations, and mentor engineers.

Lead bring-up, deployment, and optimization of full-chip and system-level emulation platforms. Build models, transactors, and BFMs; optimize emulation performance; enable HW/SW co-development; support DV, firmware, silicon bring-up, and cross-functional debug; maintain automation and CI for regression and compile flows.

Lead full physical design flow for complex SoC blocks and top-level integration from synthesis to GDSII. Drive timing closure, PPA optimization, physical sign-off (DRC/LVS, IR drop, EM), ECOs and tapeout. Collaborate with front-end, verification, DFT, packaging teams and external vendors, develop automation and methodology, and support products through production and spaceflight.

Lead end-to-end RTL-to-GDSII physical design for high-performance SoCs in advanced FinFET nodes. Own synthesis, floorplanning, P&R, CTS, STA, DRC/LVS and sign-off; develop methodologies and automation to optimize PPA; drive timing closure, coordinate package/SI/PI and DFT, manage external PD partners and EDA tool flows, and support post-silicon bring-up and production for spaceflight-qualified designs.

Lead verification of custom ASIC/SoC from block to full-chip: develop verification plans, build SystemVerilog/UVM testbenches, run constrained-random and directed tests, use SVA and formal methods, manage regressions and CI, drive coverage closure, support post-silicon bring-up, and influence DV methodology across cross-functional teams.

Lead DFT architecture and implementation for complex mixed-signal SoCs. Responsible for RTL-level scan and BIST insertion, ATPG flow development and coverage closure, mixed-signal test strategies, DFT verification and signoff, silicon bring-up support, and methodology/automation improvements while collaborating with design, verification, and physical design teams.

Define and execute verification plans for block-to-full-chip ASICs using SystemVerilog/UVM. Build testbenches, assertions, constrained-random and directed tests, manage regressions and CI, run simulations, triage failures, close coverage, and support silicon bring-up and post-silicon debug while collaborating across architecture, RTL, DFT, firmware, and physical design teams.

Own FPGA prototyping and silicon bring-up for next-generation communications ASICs. Build FPGA-based platforms, support first-silicon debug, validate high-speed interfaces, develop automated test infrastructure, and collaborate across ASIC, firmware, software, and systems teams.