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Develop and enhance the CUDA Quantum platform, focusing on inter-device communication and toolchain integration for hybrid quantum-classical systems, while collaborating with cross-functional teams to solve complex computing challenges.

The Senior Formal Verification Engineer will verify ASICs using formal verification methods, ensuring correctness and collaborating with architects and designers across projects.

The Senior Physical Design Engineer will lead full-flow chip design, optimize PPA, execute tapeout, and innovate design methodologies by collaborating across teams.

The role involves driving go-to-market strategies, creating technical marketing content, and fostering a community around quantum products.

As a Senior ASIC Design Engineer, you will design high performance RTL, collaborate with teams, and analyze architectural trade-offs for ASICs and GPUs.

Develop software for the CUDA-Q platform, focusing on quantum error correction and AI algorithms for quantum applications while improving CI/CD pipelines and collaborating with teams.