Top Tech Jobs & Startup Jobs in Seattle, WA

Own end-to-end mechanical design of outdoor radar sensor nodes, including array panels, enclosures, thermal systems, ruggedization, and manufacturing readiness. Lead thermal and structural analysis, qualification testing, tooling, fixtures, vendor management, and cost reduction. Collaborate with RF, antenna, electronics, and systems engineers to define interfaces and deliver designs from concept through production.

Develop embedded firmware and Linux software for phased-array communications and radar systems. Build MCU-FPGA interfaces, device drivers, control and telemetry features, calibration tools, and automated test software. Bring up hardware in the lab using debugging and measurement equipment, collaborate with RF, FPGA, DSP, and hardware engineers, and help establish software development practices including code review, CI, version control, and documentation.

Own full-cycle recruiting for technical and non-technical roles, including sourcing, screening, coordination, offers, and closing. Build recruiting processes, implement an ATS, develop specialized engineering talent pipelines, partner with hiring managers, manage candidate communications, track recruiting metrics, coordinate agencies, support compensation benchmarking, and assist with onboarding. The role is on-site in the Seattle area and may involve export-controlled information.

Own synthesis, SDC constraints, and static timing sign-off for phased-array ASIC and FPGA designs. Drive multi-mode, multi-corner timing closure, ECOs, formal verification, and collaboration with RTL, DSP, DFT, and physical design teams. Support floorplanning, timing budgets, lab bring-up, technical strategy, documentation, and mentoring for high-performance beamforming and adaptive data paths.

Own the architecture, RTL implementation, synthesis, timing strategy, validation, and bring-up of digital subsystems for phased-array products. Lead beamformer control, interfaces, calibration, datapaths, verification methodology, and technical risk management from architecture through silicon or FPGA validation. Establish design standards, mentor RTL engineers, collaborate with RFIC, antenna, and DSP teams, and contribute to technical strategy, customer discussions, and hiring.

Owns block- and chip-level ASIC physical design from netlist through GDS, including floorplanning, power planning, placement, CTS, routing, timing closure, physical verification, EM/IR sign-off, ECOs, and FPGA P&R support. Collaborates with RTL, synthesis, STA, and DFT teams, integrates memories and interfaces, supports validation, and contributes to technical strategy and mentoring for phased-array products.

Owns end-to-end Design-for-Test architecture and implementation for phased-array ASIC and FPGA products, including scan, compression, MBIST, LBIST, JTAG, ATPG, gate-level verification, timing constraints, silicon bring-up, and ATE validation. Partners across RTL, synthesis, physical design, and test engineering to improve coverage, yield, test cost, and product quality. Automates DFT flows, supports diagnosis, and mentors team members.

Own digital RTL design for phased-array systems, including beamformer control, calibration logic, interfaces, and high-speed data paths. Drive designs from architecture through synthesis, timing closure, place-and-route support, and ASIC or FPGA validation. Perform simulation, lint, CDC analysis, and verification collaboration. Partner with RFIC, antenna, and DSP teams, support lab bring-up, improve design methodology, review peer designs, and mentor junior engineers.

Design RF and microwave systems for phased arrays, communications, and radar applications from architecture through production. Responsibilities include system modeling, link and line-up budgets, RF circuit and module design, simulations, characterization data analysis, and design iteration. The role collaborates with RFIC, antenna, digital, DSP, mechanical, thermal, and PCB teams to meet performance, packaging, thermal, grounding, and signal-integrity requirements.

Design RFIC beamformers and RF/mm-wave building blocks from architecture through tape-out and silicon validation. Perform circuit and system simulations, collaborate with antenna, digital, and DSP teams, and support laboratory characterization, debugging, and design iteration. Contribute to design reviews, documentation, and technical direction for phased-array communications and radar systems.